surya.narada.systems

R3: substrate liberation, mapped

Sweep executed 18 August 2026. The finding: ELO/IMM is physically demonstrated — 13 µm epitaxial stacks at ~31% AM0 and >3,000 W/kg, film-laminated flight heritage since 2009 — but the economic thesis is undemonstrated on every leg. The binding constraint is per-cycle reconditioning cost and process throughput, not reuse cycle count; and the "~10 reuse cycles" threshold in the originating article traces to a modeling assumption, not an experiment.

Why this map exists

R3 is the only direction that attacks the germanium chokepoint while keeping III-V performance: lift the junction off the wafer, reuse the wafer as a template. The originating article poses three sub-questions — ELO throughput and yield at industrial scale, substrate reuse cycle count (~10 cycles as the order-of-magnitude threshold), and IMM mechanical reliability without the handle wafer — and sets the win condition: reuse economics close at constellation volumes. Four parallel sweeps (throughput, reuse, mechanical, player claims) mapped what is actually on the record.

Throughput: hours per wafer, and no yield data anywhere

ProcessBest published evidenceImplied per-wafer timeClass
Classic HF ELO (AlAs sacrificial)0.1–0.3 mm/h lateral undercut; diffusion-limited by H₂ out-diffusion through the narrowing gap (van Niftrik/Schermer model)~250 h per 6-inch wafer (derived)physics ceiling
Stressor-assisted wet ELO15 mm/h (Ramu 2022, InGaAs + PMMA stressors); 20 mm/h reported as fastest (Tampere dissertation 2025)~3.75–5 h per 6-inch wafer (derived)laboratory
Mechanically gap-opened ELO~10 mm/h typical, 30 mm/h best claimed (apparatus-dependent)~2.5–7.5 h per 6-inch wafer (derived)laboratory
Gas-phase XeF₂ (Ge sacrificial)3–9 mm/h on 1 cm² coupons, room temperature, selectivity ~10⁶ (Cole, TU Wien)not wafer-scalelaboratory
MicroLink production platform6-inch GaAs platform claimed; AIXTRON 8×6-inch reactor ordered 2011no published throughput, cycle time, or yieldcompany claim

established The scale gap is derivable: 10,000 m²/yr of constellation demand is ≈565,000 six-inch wafer lift-offs per year, ≈1,550 per day. At the fastest published etch rates that is on the order of 160–260 etch stations running continuously — before yield losses. No public evidence shows any ELO facility at even 1% of that throughput, and no source anywhere publishes ELO process yield. Alta Devices ran an ELO pilot/production line and failed commercially (closed 2019; equipment auctioned).

Reuse: the "~10 cycles" threshold is an assumption

Substrate / routeDemonstratedCaveat
GaAs, classic ELO4 reuses, no degradation in film lifetime/mobility (van Geelen 1997)materials metrics only, no device curve
InP, protection-layer ELO1 reuse, no device degradation (Lee/Forrest 2010)single cycle
GaAs, protection layers“Repeated use,” no repolish needed (Lee 2012); “indefinite” claimed, count not stated (Lee 2014); direct reuse without post-processing (Cheng/IBM 2013)count not published
GaAs, IMM cells (MicroLink)“Multiple substrate reuses” demonstrated (Adams 2013, IEEE J. PV)count paywalled/unstated
GaAs, water-soluble sacrificial“Multiple reuses,” no CMP, no degradation (Sharma 2022)count not extractable
Ge, porous-Ge PEELER1 reuse demonstrated; RMS roughness 20.1→1.3 nm after wet reconditioning; ~30 projected (Paupy 2023)projection, not demonstration
Ge, controlled spalling49 cells on spalled 50 mm Ge, best 23.4%, no CMP (Mangum 2022)spalling, not classic ELO

The correction: the originating article's "~10 reuse cycles is the threshold where germanium exposure drops by an order of magnitude" is arithmetically true but experimentally unsupported. The figure circulates in LCA and cost literature as an assumption — one peer-reviewed LCA states "5 to 10 wafer reuses have already been achieved" citing Adams 2013 and Lee 2012, whose own demonstrated counts are lower or unstated — and NREL's cost modelsassume 10–100 reuses to show competitiveness. The strongest demonstrated counts are 4 (GaAs, 1997, materials metrics only) and 1 (Ge, 2023). Ge reuse after classic AlAs-sacrificial ELO is undemonstrated entirely; the demonstrated Ge routes are porous-Ge and spalling, one cycle each.

established And the cycle count is not the binding variable anyway. NREL's bottom-up techno-economic analysis (Ward 2016) of all three substrate-liberation strategies — ELO, spalling, porous-Ge — found cost reduction is limited "not by the number of reuse cycles achievable, but by the costs incurred in each cycle to prepare the substrate for another epitaxial deposition": CMP reconditioning at an estimated 10–40 µm and $9–34 per cell per cycle, against a substrate that costs >$30/W. Protection-layer schemes that eliminate CMP exist in the literature (Michigan, IBM, Houston) but have no published per-cycle device-performance series.

Mechanical: what holds the cell together

established Two demonstrated answers: metal carrier stacks (ISE/tf2's IMM4J uses the back-contact metal as the mechanical carrier — 13 µm total stack, 140 g/m², 30.9% AM0; Radboud transfers to ~20 µm Au or ~25 µm Cu) and polymer/silicone laminates (JAXA's Space Solar Sheet: IMM-3J strings in silicone between films, <0.2 mm total, ~600 W/kg at sheet level, >150 W/kg at paddle level, internal qualification tests passed within ±2.5% with no crack propagation). The ELO peel-bend itself does not damage devices (Radboud accelerated ageing). What does damage them: handling of unsupported films (cracks and shunts documented in the ISE IMM4J work) and copper carriers under thermal stress (>60% efficiency loss after 37 days at 200 °C from Cu diffusion, vs ~10% for gold).

gap No published AIAA S-111/S-112 or ECSS-E-ST-20-08C qualification campaign exists for any substrate-free thin-film III-V cell or laminate — qualified metamorphic products (SolAero Z4J, IMM-β) retain or do not disclose their substrate. No cyclic-flexure dataset (bend radius vs cycles vs ΔP) exists for IMM/ELO cells; MicroLink's "2 cm bend radius" is unsourced marketing. No vibration, acoustic, or shock data. No on-orbit degradation data for substrate-free multijunction III-V: the only orbital thin-film III-V data point is JAXA's 2009 film-laminated dual-junction demonstration, and MicroLink's extensive Zephyr heritage is stratospheric — a materially different environment with no high-energy particle radiation and no thermal-vacuum cycling.

Player landscape

PlayerDemonstrated / claimedScale evidenceHonest caveat
MicroLink Devices37.75% AM1.5G 3J ELO cell, NREL-certified, 6-inch platform (2018); production datasheet 29% AM0, <350 g/m², >1000 W/kg UAV cellsZephyr S HAPS 25-day flight (2018), Zephyr 8 64-day (2022); PHASA-35 production contractAll scale/yield/cost numbers unpublished; AM0 >3000 W/kg uncertified; stated it “will begin” AIAA S-111/112 space qualification only in Jan 2021; no on-orbit heritage found
Rocket Lab / SolAeroIMM-α 32.0% min avg BOL in production; IMM-β ~33.3% BOL, 87% power remaining at 10¹⁵ e/cm², listed as space-qualified 5J productVolume production of substrate-removed IMM cells; $80M acquisition (2022); $23.9M CHIPS award (2024)Removes the substrate but claims no reuse and no ELO — liberation from substrate mass, not from substrate consumption
AZUR SPACEGe-substrate 3G30/4G32 lines; no ELO product or position foundESA EUOG study: recycles Ge from backgrinding waste, >90% recovery target (~80% reported implemented 2021)Answers the chokepoint with recycling, not lift-off
Fraunhofer ISE / tf2IMM4J thin-film: 13 µm stack, 140 g/m², >3000 W/kg, 30.9% AM0 BOL (peer-reviewed); EpiWafer reusable-template program with licensable patentsLaboratoryNo published ISE ELO cell or reuse-cycle data; handling cracks documented in unsupported films
NRELIMM architecture origin (40.8% at 326 suns, 2008); TEAs anchoring the cost picture; spalling and Ge-on-nothing demosResearch + tech transfer (exclusive IMM license to MicroLink)GON route at 14.4% — lab-to-industry gap runs in industry's favor here
Umicore / ESA-ELLA200 mm engineered Ge substrates (Ge-on-nothing, porous Ge); wafer reused 2×; 3J cells on 7 µm Ge foil ≈ controlsGovernment-contracted feasibilityLab scale; no production intent stated

Cost anchors: current III-V cells run ~$150/W (Schulte 2023); the substrate alone is >$30/W. No public $/W price exists for any ELO-based product — MicroLink claims only qualitative "lower manufacturing costs." NREL's conditional pathway to $0.40/W requires high-volume production and low-cost epitaxy andsubstrate-reuse R&D simultaneously.

The gaps, as fundable work

  1. ELO process yield at any scale — the single largest evidence gap; no public number exists.
  2. Per-wafer lift-off time in a real line — only coupon-scale lateral etch rates are published; all per-wafer times here are derived arithmetic.
  3. Demonstrated reuse with per-cycle device data — a published "N reuses at constant AM0 efficiency" curve, most valuable for Ge after classic ELO (currently undemonstrated).
  4. Space qualification of substrate-free product — an AIAA S-111/ECSS-class campaign for a lifted cell or laminate, including the missing cyclic-flexure and thermal-vacuum datasets.
  5. ELO product $/W — any verified price or cost breakdown for a shipped ELO cell.
  6. MicroLink space-qualification follow-through — the company announced AIAA S-111/112 work in 2021; no completion evidence found. Watch item, alongside Rocket Lab IMM process disclosures.

What this changes

R3 stays on the board, but reframed: the question is no longer "can the wafer be reused ~10 times" but "can per-cycle reconditioning cost and per-wafer throughput fall far enough that reuse beats both virgin Ge and AZUR-style Ge recycling." The substrate-liberation physics is real and flying (stratospherically); the economics are unbuilt, and the volume player in the market (Rocket Lab/SolAero) has voted with its process: substrate removal without reuse. The most decision- relevant single artifact would be MicroLink's actual per-wafer economics — not public — followed by a demonstrated multi-cycle Ge reuse series with device data, which any lab could produce.

Perimeter and provenance

Four parallel literature sweeps, 32 sources, admitted to the Surya epistemic graph as event ev-000000000010 with assessmentsurya-assessment-r3-gap-map-2026-08, judgmentestablished-with-gap. Flagged honestly: the two most-cited reuse papers (Bauhuis 2010, Adams 2013) are paywalled and their cycle counts are known only through secondary paraphrase; the Tampere dissertation full text is bot-walled (20 mm/h figure from the abstract); conflicting "fastest etch rate" claims exist across sources under non-comparable conditions; the JAXA qualification test matrix (temperatures, cycle counts) could not be extracted from the proceedings PDF; per-wafer times and constellation throughput are derived arithmetic, labeled as such; MicroLink scale figures are company claims throughout, with only the 37.75% AM1.5G efficiency independently certified.

Sources